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dc.contributor.author | Molinar Solis, Jesús Ezequiel | |
dc.contributor.author | SANCHEZ GASPARIANO, LUIS ABRAHAM | |
dc.contributor.author | GARCIA LOZANO, RODOLFO ZOLA | |
dc.contributor.author | PONCE PONCE, VICTOR HUGO | |
dc.contributor.author | OCAMPO HIDALGO, JUAN JESUS | |
dc.contributor.author | MOLINA LOZANO, HERON | |
dc.contributor.author | DIAZ SANCHEZ, ALEJANDRO | |
dc.creator | Molinar Solis, Jesús Ezequiel; 38397 | |
dc.creator | SANCHEZ GASPARIANO, LUIS ABRAHAM;x1232925 | |
dc.creator | GARCIA LOZANO, RODOLFO ZOLA; 91605 | |
dc.creator | PONCE PONCE, VICTOR HUGO; 35257 | |
dc.creator | OCAMPO HIDALGO, JUAN JESUS; 231564 | |
dc.creator | MOLINA LOZANO, HERON; 202593 | |
dc.creator | DIAZ SANCHEZ, ALEJANDRO; 8120 | |
dc.date.accessioned | 2016-03-16T17:17:56Z | |
dc.date.available | 2016-03-16T17:17:56Z | |
dc.date.issued | 2011 | |
dc.identifier | http://www.redalyc.org/articulo.oa?id=61520765004 | |
dc.identifier.uri | http://hdl.handle.net/20.500.11799/39483 | |
dc.description.abstract | In this paper, a low-complexity current-mode Winner-Take-All circuit (WTA) of O (n) complexity with logical outputs is presented. The proposed approach employs a Quasi-FG Inverter as the key element for current integration and the computing of the winning cell. The design was implemented in a double-poly, three metal layers, 0.5µm CMOS technology. The circuit exhibits a good accuracy-speed tradeoff when compared to other reported WTA architectures. | es |
dc.format | application/pdf | |
dc.language.iso | eng | es |
dc.publisher | Instituto Politécnico Nacional | |
dc.relation | http://www.redalyc.org/revista.oa?id=615 | |
dc.rights | openAccess | |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0 | |
dc.source | Computación y Sistemas (México) Num.3 Vol.14 | |
dc.subject | computación | |
dc.subject | winner-take-all | |
dc.subject | neural networks | |
dc.subject | analog circuits | |
dc.subject.classification | INGENIERÍA Y TECNOLOGÍA | |
dc.title | A low-complexity current-mode WTA circuit based on CMOS Quasi-FG inverters | es |
dc.type | Artículo | |
dc.provenance | Científica | |
dc.road | Dorada | |
dc.ambito | Internacional | es |
dc.audience | students | |
dc.audience | researchers | |
dc.type.conacyt | article | |
dc.identificator | 7 |
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